Please note that this signpost is now closed to new applications in order that we are able to process requests before May 2010. The ICT programme will soon be announcing a new notice in its place.
Two areas make up the current ICT signposting list: grand challenges in microelectronic design and grand challenges in silicon technology. Both areas are signposted until 1 May 2010. Up to 10% of the ICT programme budget is available for signposted areas depending on the quality of proposals submitted.
Grand Challenges in Microelectronic Design
We want to encourage proposals tackling any of the four grand challenges identified through a consultation carried out in 2007-08:
- GC1 Batteries not included: minimising the energy demands of electronics
- GC2 Silicon meets life: interfacing electronics to biology
- GC3 Moore for less: Performance-driven design for next-generation chip technology
- GC4 Building brains: Neurologically-inspired electronic systems
Contributing technologies and scientific areas have been identified for each grand challenge so we expect proposals to be multidisciplinary as appropriate.
More information: Grand Challenges in Microelectronic Design report and roadmap
Grand challenges in Silicon Technology
We want to encourage proposals in any of the first three grand challenges identified through a consultation carried out in 2007-08:
- GC1 Novel devices and processes using silicon-based technologies
- GC2 Modelling and simulation for silicon-based technologies
- GC3 Characterisation for silicon-based technologies
Four further grand challenges were identified, which lie partly outside the remit of the ICT programme:
- GC4 New materials for silicon-based technologies
- GC5 Smart nano: nanoscience to nanoengineering
- GC6 Silicon for life: towards next-generation healthcare
- GC7 Eco-silicon: energy
Please contact us before submitting a proposal to make sure that your proposed research is within the remit of the signposting.
More information: Grand challenges in Silicon Technology report and roadmap
Does your proposal fit with the signposted areas?
If you’re not sure whether your proposal falls into either of the signposted areas, please send us a two-page outline of your proposal. This should contain the objectives, summary and beneficiaries of your project and a rough estimate of cost.
Please email the outline to:
• Microelec@epsrc.ac.uk - for grand challenges in microelectronics
• SiliconNano@epsrc.ac.uk - for grand challenges in silicon technology
We will reply with feedback and advice on how to take your proposal forward within 10 days of receiving your email.
Background to signposting and grand challenges
Community-led grand challenges are a way of identifying long-term (10-20 year) engaging problems or emerging research themes that require collaborations across many research areas. We use signposting to highlight priority research areas in responsive mode instead of issuing calls for proposals.
Signposting of the grand challenges in microelectronics and silicon technology follows consultations with the research community and industry early in 2008. We also held a workshop in March 2008 with the Electronics Knowledge Transfer Network (e-KTN) to disseminate the microelectronics grand challenges to industry and to start building collaborations. The e-KTN has highlighted the microelectronics grand challenges as one of their priority themes, and more workshops are planned for 2008.
You are welcome to suggest a possible research area for signposting at any time. We aim to signpost areas for at least 18 months and have no more than three areas on the list at any time.
See also: